A charge-pump circuit is a type of circuit configured to provide a voltage with a high voltage level that is either more positive than a power supply voltage (referred to as a high positive voltage) or has a reverse polarity with respect to the power supply voltage (referred to as a high negative voltage). In many circuit applications, both the high positive voltage and the high negative voltage are required, and it is common for these voltages to be generated on-chip.
The charge pump circuit works using a basic building block referred to as a “voltage doubler”. For a positive charge pump, the voltage doubler circuit takes a DC input voltage (VDD) and outputs a double DC output voltage. By cascading N voltage doubler stages in series, a final output voltage can be reached that is substantially equal to (N+1)*VDD. For a negative charge pump, the voltage double circuit takes a ground input voltage (GND) and provides −VDD as the output voltage. By cascading N voltage doubler stages in series, a final output voltage can be reached that is substantially equal to −(N*VDD).
A common approach is to use two different charge-pump circuits to generate the desired positive voltage and negative voltage. A consequence of this approach is that the circuitry needs many on-chip capacitors that occupy a large area and the capacitors must be separately placed for each of the positive and negative charge-pump circuits. In addition, each charge pump circuit requires its own voltage regulator circuit in order to regulate the output voltage of each charge-pump at the desired positive and negative voltage level. The voltage regulator circuit typically requires resistors (for use in a voltage detection circuit) which, like the capacitors, occupy a large area and these resistors also must be separately placed for each charge pump.
It is known in the art to design a voltage doubler circuit that is operable to either generate the high positive voltage or the high negative voltage. An example of such a circuit is shown in FIG. 1 and is referred to in the art as a latch-based voltage doubler. The latch is formed by two cross-coupled CMOS inverter circuits 10 and 12. The source terminals of the p-channel MOS transistors of the latch circuit are connected to node B and the source terminals of the n-channel MOS transistors of the latch circuit are connected to node A. A capacitor is coupled to each pair of connected drain terminals of the MOS transistors of the latch circuit. A first capacitor coupled to inverter circuit 10 is configured to receive a clock signal CK and a second capacitor coupled to inverter circuit 12 is configured to receive a clock signal CKN (which is a logical inversion of the clock signal CK).
When the latch-based voltage doubler circuit is to be used as a positive voltage doubler, a positive supply voltage VDD is connected to node A and a high positive voltage of 2*VDD is generated at node B. Conversely, when the latch-based voltage doubler circuit is to be used as a negative voltage doubler, the ground supply voltage GND is connected to node B and a high negative voltage of −VDD is generated at node A. By cascading N latch-based voltage doubler circuits of FIG. 1 in series, the resulting charge pump circuit can generate, in ideal conditions with no current load and no conduction loss, the following voltage levels:
Vout=(N+1)*VDD; when connected in a positive high voltage configuration;
Vout=−N*VDD; when connected in a negative high voltage configuration.
In comparison to other prior art voltage doubler circuits well known to those skilled in the art, the latch-based voltage double circuit of FIG. 1 advantageously does not exhibit a threshold voltage drop across the connected stages of the charge pump. Furthermore, the circuit requires just the two clock phases (CK and CKN). However, the latch-based voltage doubler circuit does have the following problems:
a) each stage works well for generating the high positive voltage, but operation is not satisfactory when configured to generate the high negative voltage due to the presence of p-channel MOS transistors in the circuit. When negative voltages are to be generated, then the n-type well (body) for the p-channel MOS transistors are biased to the ground supply voltage level or ideally at a positive voltage level such as VDD. So, it cannot be connected to the local source terminal of the p-channel MOS. Otherwise, the n-type well to substrate junction can be forward biased and there will be functionality failure (see, FIG. 1, circuit 14);
b) due to biasing of the p-channel MOS transistors in body-effect, the n-type well to source/drain junctions are under a high voltage stress. With an increase in the number N of cascaded stages, this stress correspondingly increases and there can be reliability issues in negative voltage generation;
c) due to the fact that the p-channel MOS transistors need to be biased in body-effect, the threshold voltage of p-channel MOS transistors will increase with each cascaded stage of the N stage charge pump causing a reduction in the efficiency of charge-pump operation in negative voltage generation mode; and
d) there is a limitation that the n-type well is to be biased to GND/VDD during negative voltage generation, but connected locally to the source terminal during positive voltage generation. So, for the circuit to be operational in both positive and negative voltage mode, additional circuitry is required to switch the biasing of the n-type well.
There is a need in the art for a voltage doubler circuit, suitable for use in positive and negative charge pumps, that can be used to generate either a positive or negative output voltage without compromising circuit reliability and performance.